The present invention relates to a method of manufacturing a semiconductor device, and to a technique effective when applied, for example, to a manufacturing technique of a semiconductor device using an SOI substrate.
One of the characteristics required of a MISFET (Metal Insulator Semiconductor Field Effect Transistor) formed on a semiconductor substrate is to reduce leakage current. In a MISFET having a gate length of 90 nm or less, it is particularly important to suppress GIDL (Gate Induced Drain Leakage), one of the items of leakage current. For example, Patent Document 1 discloses, as measures against leakage current due to such GIDL, a technique in which an extension region is separately formed in a region having a high concentration that is formed at a deep position and a region having a low concentration that is formed at a shallow position.
Meanwhile, there is a technique of forming a MISFET on an SOI (Silicon On Insulator) substrate, as a semiconductor device for low power consumption. For example, Patent Document 2 discloses a technique in which a MISFET formed on an SOI substrate and a MISFET formed on a semiconductor substrate are separately formed in the same semiconductor chip.